IET Computers and Digital Techniques

IET Computers and Digital Techniques 由 Wiley 出版，属中科院计算机科学大类（2025 升级版4区）。按 OpenAlex 近年发文统计，该刊主要发表 VLSI and Analog Circuit Testing、Parallel Computing and Optimization Techniques、Low-power high-performance VLSI design 等主题的论文，这 3 个主题约占 31.1%，主导子领域为 Electrical and Electronic Engineering、Hardware and Architecture。（根据 OpenAlex 主题统计与中科院分区数据生成）

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.

来源：LetPub

研究方向（LetPub）：工程技术-计算机：理论方法

主编 Anirban Sengupta出版商官网

编委会国家分布：中国大陆 4 位（约 10%）；主要国家 印度 12、英国 5、中国 4、意大利 3、美国 2（共 40 位编委标注了国家） 编委会 ↗出版商官网 · 2026-10-03

中科院期刊分区表

数据库收录

SCIEScopusDOAJLetPub

国际期刊预警名单：各版本均未列入LetPub

不同版本、大类与小类分别展示，不将不同评价口径合并为一个分区值；投稿与考核前请确认所在机构采用的版本。

影响力指标

影响因子

1.05LetPub · 2026-09-13

CiteScore 2026-06

2.6LetPub · 2026-09-13

SJR 2026-06

0.2LetPub · 2026-09-13

SNIP 2026-06

0.38LetPub · 2026-09-13

h-index

40LetPub · 2026-09-13

h-index

37OpenAlex · 2026-10-01

i10-index

215OpenAlex · 2026-10-01

两年平均被引

1.03OpenAlex · 2026-10-01

自引率

0%LetPub · 2026-09-13

Gold OA 文章占比

100%LetPub · 2026-09-13

发文规模

年文章数

9LetPub · 2026-09-13

不同来源的统计口径与观测时间不同，页面保留各来源原值；“出版商公布”为期刊官网自述数据。

其他来源

平均审稿速度（社区反馈）

>12周，或约稿LetPub · 2026-09-13

平均录用比例（社区反馈）

容易LetPub · 2026-09-13

投稿到发表（期刊自报）

约 31 周DOAJ · 2026-10-11

评审方式

单盲同行评审DOAJ

社区反馈来自投稿者样本，置信度 0.5，不代表期刊承诺；“出版商公布”的时间节点定义以官网为准。

• APC 费用说明 ↗DOAJ
• 费用减免政策 ↗DOAJ
• 开放获取声明 ↗DOAJ
• 许可与版权 ↗DOAJ

费用以期刊官网为准；不同来源的观测时间可能不同，页面保留各来源原值，不做平均。

出版商

Wiley

出版国家或地区

ENGLAND

出版语言

English

出版周期

Bi-monthly

创刊年份

2007

ISSN

1751-8601

电子版 ISSN

1751-861X

官方链接

• 期刊主页 ↗DOAJ
• 投稿系统 ↗LetPub
• 作者指南 ↗DOAJ
• Aims & Scope ↗DOAJ
• 专刊 / 特刊征稿 ↗出版商官网
• APC 费用说明 ↗DOAJ
• 费用减免政策 ↗DOAJ
• 开放获取声明 ↗DOAJ
• 许可与版权 ↗DOAJ
• 评审流程 ↗DOAJ
• 编委会 ↗DOAJ
• 查重政策 ↗DOAJ